Designing encoders and decoders for error-correcting codes requires knowledge of coding theory, can be confusing and decisions about which code to implement and how to design the encoder and decoder are difficult.

This site will be designed with the objective of helping everyone gain the knowledge and understanding needed to make their own choices about which error-correcting code to use and how to design the encoder and decoder.

Designers of encoders and decoders face difficult challenges.  In order to end up with an actual, practical implementation, many difficult decisions need to be made.  Designing is really a matter of making a long sequence of decisions like what code to use, what algorithms to use, what logic to use, what architecture to implement, what chip to use, etc.  These decisions are difficult.

The role of a coding theorist or researcher is much different from the role of a digital logic designer or implementer.  The theorist is interested in finding new insightful truths that can be proven.  The role of the theorist is important because without theorists there would be no information or coding theories and no codes to implement.  However, having many textbooks and hundreds or thousands of published papers about many different types of codes and coding topics makes the job of the logic designer difficult because they must determine which papers and topics are important and relevant and which ones are not.

This site was created to provide a place for designers to learn more about coding theory, more about what options are available and about the practical aspects of designing encoders and decoders which are usually implemented in digital logic and eventually implemented in FPGAs or ASICs.

Hopefully, this site will become a useful resource for everyone involved in the design of error-correction circuits and a site many people will bookmark and come back to frequently.

This site will focus on the following codes and implementations that are of most interest to modern designers...

  • Low-Density Parity-Check (LDPC) Codes
  • Reed-Solomon (RS) Codes
  • Binary BCH (BBCH) Codes
  • Parallel RS (PRS) Implementations
  • 2D-RS or RS Product Codes
  • 2D-RS with Iterative Decoding
  • Conventional RAID Systems

This site initially is being developed using Google Sites.  If there is considerable interest in the site, a more robust version will probably be developed.